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How to set BLSP 11 as a UART?

Questions and discussions related to Inforce 6601™ development kit

by kim760407 » Wed Feb 28, 2018 6:29 am

Hi. I would like to set BLSP 11 as a UART. It looks like this BLSP can be set to SPI/UART/I2C/UIM according to the BLSP_on_Snapdragon-820_v1.pdf. I started looking at the document "Configure a BLSP Port on APQ8096 Device", but it is unclear how to change BLSP 11. I think that I am looking at the correct msm8996.dtsi for the snapdragon 820. It looks like in this file BLSP11 is configured as a SPI as default:
spi_11: spi@75BA000 { /* BLSP2 QUP6 */
compatible = "qcom,spi-qup-v2";
Is this true? Or am I looking in the wrong location (incorrect file)?
The Inforce_6601_Development_Kit_User_Guide (Table 14 Expansion Connector 1) lists BLSP11 as an I2c, but I don't know if this is the default or not:
Pin Primary Functions Other Functions
18 BLSP11_I2C_SCL CAM2_MI2S_D1 I2C for SMB210 (DNP)
CODEC_MCLK CODEC_MCLK /SPKR_I2S_MCLK(DNP)

Could I get some help, please, setting BLSP11 to a UART? I am using Debian linux for development.
Thanks,
Kim
kim760407
 
Posts: 16
Joined: Thu Jan 04, 2018 7:51 am

by ashwin » Mon Mar 05, 2018 5:56 am

Hi

Please refer the document. There is a section to configure the BLSP as UART as well
Following is a sample patch for uart on blsp11.

Hope this helps.

Code: Select all
From c60db1c67d2361d9b5c3ddf05aff554fd862a9ea Mon Sep 17 00:00:00 2001
From: Inforce Computing <inforce@inforcecomputing.com>
Date: Fri, 22 Dec 2017 12:43:46 +0530
Subject: [PATCH] enable_uart11

Change-Id: I50154c92bc29860b5191dbe0b317441db0ba35a4
---
 arch/arm/boot/dts/qcom/apq8096-sbc.dtsi     |  4 ++++
 arch/arm/boot/dts/qcom/msm8996-pinctrl.dtsi | 14 ++++++++++++++
 arch/arm/boot/dts/qcom/msm8996.dtsi         | 19 +++++++++++++++++++
 3 files changed, 37 insertions(+)

diff --git a/arch/arm/boot/dts/qcom/apq8096-sbc.dtsi b/arch/arm/boot/dts/qcom/apq8096-sbc.dtsi
index 9e9c365..e6ea94e 100644
--- a/arch/arm/boot/dts/qcom/apq8096-sbc.dtsi
+++ b/arch/arm/boot/dts/qcom/apq8096-sbc.dtsi
@@ -45,6 +45,10 @@
    pinctrl-0 = <&uart_console_active>;
 };
 
+&uart3 {
+    status = "ok";
+};
+
 &uart2 {
    status = "ok";
 };
diff --git a/arch/arm/boot/dts/qcom/msm8996-pinctrl.dtsi b/arch/arm/boot/dts/qcom/msm8996-pinctrl.dtsi
index 07123f3..f879181 100644
--- a/arch/arm/boot/dts/qcom/msm8996-pinctrl.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8996-pinctrl.dtsi
@@ -205,6 +205,20 @@
          };
       };
 
+        blsp2_uart5_active: blsp2_uart5_active {
+            mux {
+                pins = "gpio58", "gpio59";
+                function = "blsp_uart11";
+            };
+
+            config {
+                pins = "gpio58", "gpio59";
+                drive-strength = <2>;
+                bias-disable;
+            };
+        };
+
+
       blsp2_uart6_active: blsp2_uart6_active {
          mux {
             pins = "gpio85", "gpio86";
diff --git a/arch/arm/boot/dts/qcom/msm8996.dtsi b/arch/arm/boot/dts/qcom/msm8996.dtsi
index c415804..1b3afdb 100644
--- a/arch/arm/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8996.dtsi
@@ -40,6 +40,7 @@
       i2c8 = &i2c_8;
       i2c12 = &i2c_12;
       spi0 = &spi_0;
+        serial3 = &uart3;
       serial2 = &uart2;
    };
 
@@ -323,6 +324,24 @@
       clock-names = "core_clk", "iface_clk";
    };
 
+    uart3:serial@075b3000 {    // BLSP11 LSUART
+        compatible = "qcom,msm-lsuart-v14";
+        reg = <0x75b3000 0x1000>;
+        interrupts = <0 117 0>;
+        status = "ok";
+        qcom,msm-bus,name = "serial_uart3";
+        qcom,msm-bus,num-cases = <2>;
+        qcom,msm-bus,num-paths = <1>;
+        qcom,msm-bus,vectors-KBps =
+                <84 512 0 0>,
+                <84 512 500 800>;
+                clocks = <&clock_gcc clk_gcc_blsp2_uart5_apps_clk>,
+                         <&clock_gcc clk_gcc_blsp2_ahb_clk>;
+                clock-names = "core_clk", "iface_clk";
+        pinctrl-names = "default";
+        pinctrl-0 = <&blsp2_uart5_active>;
+    };
+
    uart2:serial@075b4000 {    // BLSP12 LSUART
       compatible = "qcom,msm-lsuart-v14";
       reg = <0x75b4000 0x1000>;
--
1.9.1
.
ashwin
 
Posts: 36
Joined: Wed Jul 01, 2015 10:07 pm

by kim760407 » Mon Mar 05, 2018 9:29 am

Hi Ashwin,

The msm8996.dtsi file that was given in the latest debian zip is different from yours:
i2c8 = &i2c_8;
i2c12 = &i2c_12;
spi0 = &spi_0;
spi11 = &spi_11;
};
Mine has a spi11 alias, whereas yours has a serial2 alias. Also in the APQ8096-Configure-BLSP-Port-Application-Note, page 13, it talks about configuration of BLSP1 UART1. It mentions three files: <chipset>.dtsi, clock-gcc-<chipset>.c and <chipset>-pinctrl.dtsi. It does not mention a apq<chipset>-sbc.dtsi that you have in your code changes. How would I know to change this file from the application note? Do I need to make any changes to the gcc-<chipset>.c as per the Application Note? I'm just a little confused by the differences in files (application note versus files you mentioned).
Thanks,
Kim
kim760407
 
Posts: 16
Joined: Thu Jan 04, 2018 7:51 am

by kim760407 » Wed Mar 07, 2018 1:02 pm

Hi Ashwin,
I patched the files you mentioned, but I'm not sure if anything changed in the system. How can I verify that BLSP11 is now a uart? I looked in /dev folder but everything looks the same to me. Which /dev/tty? is the correct device for BLSP11?
Also in the documentation, it is mentioned to cd /sys/kernel/debug/msm-bus-dbg/client-data and do an "ls" command to see the device name, but I do not see "serial_uart3" when I issue the "ls" command.

Can you also tell me where the values for the below come from? Are they documented?
reg = <0x075b3000 0x1000>;
interrupts = <0 117 0>;
Thanks,
kim
kim760407
 
Posts: 16
Joined: Thu Jan 04, 2018 7:51 am

by ashwin » Mon Mar 12, 2018 10:31 pm

Hi Kim,

The patch i provided you is using the android kernel. But the procedure is the same for debian as well.

Once you set the alias. You should be able to see the same enumerated under /dev/

eg:-

+ serial3 = &uart3;

this would enumerate as /dev/ttyHSL3

it would be HSL for low speed uart and HS for high speed uart.

Hope this helps.

Best Regards,
Ashwin
ashwin
 
Posts: 36
Joined: Wed Jul 01, 2015 10:07 pm

by kim760407 » Tue Mar 13, 2018 6:42 am

Hi Ashwin,

I am seeing a ttyHSL0 and I saw this one before adding the patches. Can you give me the list of uarts? There are 12, correct? And could you give me the "reg" and "interrupts" values for the msm8996.dtsi file I would put in for each of them to get them to work. Maybe the BLSP11 does not work.

I tried adding a different uart. serial2=&uart2 alias and this in msm8996.dtsi:
uart2: serial@07570000 { // BLSP1 LSUART
compatible = "qcom,msm-lsuart-v14";
reg = <0x07570000 0x1000>;
interrupts = <0 108 0>;
status = "ok";
qcom,msm-bus,name = "serial_uart2";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<84 512 0 0>,
<84 512 500 800>;
clock-names = "core_clk", "iface_clk";
clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>,
<&clock_gcc clk_gcc_blsp1_ahb_clk>;
pinctrl-names = "default";
pinctrl-0 = <&blsp1_uart2_active>;
};

Then when I flash the boot and reboot I see a /dev/ttyHSL1 and a /dev/ttyHSL2 but not a /dev/ttyHSL0 any longer.

Another question. How can I change the baud rate?

Thanks,
Kim
kim760407
 
Posts: 16
Joined: Thu Jan 04, 2018 7:51 am

by kim760407 » Fri Mar 30, 2018 9:18 am

The fix for me was to not add this alias:
+ serial3 = &uart3;

Then I see a /dev/ttyHSL1!
Thanks,
Kim
kim760407
 
Posts: 16
Joined: Thu Jan 04, 2018 7:51 am

by kim760407 » Fri Jun 01, 2018 2:37 pm

In the newer version of linux (buster) the instructions above do not work and I do not see serial device. Can you tell me what I could be doing wrong? I am using the apq8096-db820c.dtsi, msm8996.dtsi, and apq8096-db820c-pins.dtsi to make changes.
Thanks,
Kim
kim760407
 
Posts: 16
Joined: Thu Jan 04, 2018 7:51 am


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